This invention relates to memory controllers. More particularly, the invention relates to controllers for DRAM memories wherein pages, subpages or rows must be activated before accesses can be made to the pages, subpages or rows.
An individual memory location in a dynamic random access memory (xe2x80x9cDRAMxe2x80x9d) is specified using a row address and a column address. A particular row in a DRAM is commonly referred to as a xe2x80x9cpagexe2x80x9d of memory. It is common to organize multiple DRAM chips into multiple banks to form a larger memory system. It is also common to organize each individual DRAM chip into multiple banks internally. Further, multi-bank memory systems may be formed using chips that have multiple banks internally. In any of these kinds of multiple-bank systems, a bank address is needed in addition to a row address and column address to specify a single memory location.
Prior to accessing a target memory location in a multi-bank DRAM system, the target memory location""s host row and bank must first be activated. After the bank/row activation step has been completed, multiple accesses to columns within the activated bank/row may be performed. Prior to activating and accessing a different row within the same bank, the previously-accessed bank must be precharged. The precharge step is commonly referred to as xe2x80x9cclosingxe2x80x9d a bank/row within the DRAM. Generally speaking, one row in each bank may be active or xe2x80x9copenxe2x80x9d at any given time in a multi-bank chip. Thus, in a four-bank DRAM, four rows may be active simultaneously.
Each time an activate or precharge command is executed on a given bank, a certain amount of dead time is encountered in relation to memory accesses that could be performed on that bank. For example, after a bank/row activate command is issued to the DRAM chip, the memory controller must wait a predetermined minimum time prior to issuing reads or writes to column addresses within the activated bank/row. Similarly, the memory controller must wait a predetermined minimum time after issuing a precharge command to a bank before issuing an activate command to the same bank. The dead time that results from performing bank/row activates and precharges on the DRAM can dramatically affect the bandwidth that is available for executing memory accesses. For this reason, one of the primary concerns in memory controller design is to determine when precharge commands should be issued to the DRAM.
One prior art strategy in this regard is called the xe2x80x9caggressive prechargexe2x80x9d strategy. In a memory controller that employs the aggressive precharge strategy, memory access commands are sent to the memory controller in groups. Prior art aggressive precharge memory controllers are designed to assume that each sequential group of memory access commands will be directed to a different bank/row than was the previous group of memory access commands. For every group, therefore, when the last command in the group is being executed, the prior art aggressive precharge memory controller automatically closes the bank/row being accessed. The chief advantage of the aggressive precharge strategy is that it leaves each bank/row of the DRAM in a ready-to-activate state. When a bank/row needs to be accessed, it need only be activated; it need not be precharged and then activated.
In many DRAM chips, xe2x80x9cautoprechargexe2x80x9d memory access command types are provided. In essence, an autoprecharge memory access command is a compound command that combines a read or write burst command with a precharge command. For example, many DRAMs provide a compound burst-read-with-autoprecharge command and a compound burst-write-with-autoprecharge command in addition to simple burst read, burst write, precharge and activate commands. Most prior art aggressive precharge memory controllers make use of the compound command types in lieu of the simple command types in order to conserve memory bandwidth as much as possible.
By way of example, FIG. 1 illustrates an efficient set of sequential writes issued by an aggressive precharge DRAM controller to a dual data rate DRAM memory system. (In a dual data rate DRAM, the data bus clock speed is typically twice that of the command bus and the address bus.) In this example, four groups of writes are executed. Each sequential group is directed to a different bank of the DRAM, and each group includes four data units to be written. (For simplicity, a group size equals a burst size in this example; in the general case, a group would typically be larger than a burst size.) At time 100, an activate command A is issued to activate bank A row 0. At time 102, an activate command A is issued to activate bank B row 0. At time 104, the required minimum wait time for bank A will have passed, so a burst-write-with-autoprecharge command WP is issued to bank A column 0. This begins a four-unit burst write to bank A indicated on the data bus as DA0-DA3. While the burst write to bank A is still in progress, an activate command may be issued to bank C row 0 as shown at time 106. Thereafter, activate commands A and burst-write-with-autoprecharge commands WP can be alternated on the command bus as shown at times 108-120. Each time an activate command is issued, the corresponding bank address and row address are presented on the address bus. By alternating the banks being accessed in this manner (and by alternating the corresponding activate and write commands as shown), the bandwidth of the data bus is maximized: As can be seen in the diagram, every cycle of the data bus is utilized with write data after time 104. Generally speaking, the same result may be achieved when the group sizes are longer than a burst size. In such a case, more than one burst write would be issued for each group. By alternating the banks being accessed by sequential groups, wasted states on the data bus are eliminated.
By contrast, what happens in a prior art aggressive precharge system when two sequential groups of memory access commands are directed to the same row and bank? This condition is illustrated in FIG. 2. (The example of FIG. 2 is again simplified for illustration by assuming that a group size equals a burst size.) An activate command A for the first group is issued at time 200 to bank A row 0. The burst write starting at bank A column 0 begins at time 204 after the required activation wait time has been observed during time 202. Consistent with the behavior of prior art aggressive precharge systems, the write command issued at time 204 autoprecharges bank A. In the example being illustrated, however, the next group happens to be directed to the same bank and row as the previous group. Thus, another activate command A must be issued at time 208 to reactivate bank A row 0. The activate command issued at time 208 cannot be issued sooner because most multi-bank DRAMs do not allow an activate command to be issued to a bank while write data is being clocked into that bank. The burst write for the second group begins at time 212 after the required activation wait time has been observed during time 210. The result of having the same bank/row accessed back-to-back by two groups is that the data bus states corresponding to times 208 and 210 have been wasted. This inability to efficiently perform back-to-back same bank/row memory accesses represents a significant limitation of prior art aggressive precharge memory controllers.
It is therefore an object of the invention to improve the bandwidth efficiency of aggressive precharge DRAM memory controllers in the context of performing back-to-back same bank/row memory accesses.
In one aspect, the invention includes a modified aggressive precharge method and apparatus for controlling a DRAM or system of DRAMs. Groups of memory access commands are sent to a DRAM controller. A bank/row activate command indicator is associated with the beginning of each group, and a bank precharge command indicator is associated with the end of each group. Normally, the DRAM controller will close the bank/row corresponding to a group responsive to the bank precharge command indicator associated with the end of the group; but the DRAM controller may conditionally leave the bank/row open, as follows: The DRAM controller analyzes the command stream to determine whether first and second groups of memory access commands are directed to the same row and bank. If so, then the precharge command indicated at the end of the first group and the activate command indicated at the beginning of the second group are not executed. The effect is to leave the bank/row of the first group open so that the second group may access it without having to reopen it. Thus, dead time associated with closing and re-opening the same bank/row is eliminated while the advantages of aggressive precharge are maintained.
In a further aspect, the address of the most recently activated row is stored for each bank of the DRAM. This is done because the processing of different groups of memory accesses does not necessarily happen in a temporally contiguous manner. Each time a new bank/row activate command is indicated by the command stream, the address of the new row is compared with the address of the most recently activated row for the corresponding bank. One bit is appended to the new bank/row activate command to indicate the result of the comparison. In addition, an active/inactive status bit is maintained for each bank of the DRAM. The status bit for a bank is set when the bank is activated and is reset when the bank is precharged. When the bank/row activate command nears the point of execution, the memory controller analyzes the newly-added row comparison bit in the command as well as the status bit for the bank that corresponds to the command. If the row comparison bit is asserted and the corresponding bank is active, then the bank/row activate command is discarded instead of executed.
In a still further aspect, a count of the number of activate commands so discarded is maintained for each bank of the DRAM. Whenever an activate command is discarded, the corresponding count is incremented. Each time a precharge command indicator is encountered in the command stream, the count for the corresponding bank is analyzed. If the count is nonzero, then the precharge command is discarded instead of executed and the count is decremented. In this manner, skew that may result from queuing bank/row commands separately from bank/column commands is tracked to ensure that the number of activate commands and precharge commands discarded for a given bank will be equal. This is important because, due to the manner in which groups occur and are processed, the activate and precharge commands that form a corresponding pair may be encountered at widely separated times.
The invention has been implemented and is described herein in the context of a computer graphics memory controller. In a computer graphics system, memory accesses tend to come in groups that are bank/row coherent. This is so partly because graphics rendering data are derived from polygons that define areas, and because memory mapping schemes are generally used in graphics systems so that bank/row coherency is maintained across certain areas. (Similarly, display refresh data tend to be bank/row coherent because they are coherent along raster lines.) But the scope of the invention described and claimed herein is not limited to the computer graphics context; it will also have beneficial application in any aggressive precharge memory control system in which memory access commands tend to come in bank/row coherent groups. For example, in any computer system that uses a cache, main memory accesses will typically take the form of groups that correspond to cache misses, wherein one line of the cache maps to all or part of one bank/row in the DRAM. The ability to preserve memory bandwidth while performing back-to-back accesses to the same bank/row will enhance the performance of any such systems.